1. Field of the Invention
The invention relates to an over erase correction method, and more particularly to an over erase correction method of a flash memory array for making the over erase correction effective and saving power.
2. Description of Related Art
Flash memory is an electrical erasable and programmable read only memory (EEPROM), which has the advantages of writable, erasable, and data retention after power interrupt. Therefore, the flash memory has been broadly applied in personal computer and electronic equipment. In addition, the flash memory is a kind of a non-volatile memory and has the properties of small volume, fast access speed and low power consumption. Further, the flash memory is characterized in erasing data with a block-by-block method.
While erasing the data of the flash memory, Fowler-Nordheim (FN) tunneling is typically applied to a cell of the flash memory, which pulls electrons from a floating gate of the cell through a tunneling oxide layer to a channel region in the cell. While performing erase operation by the FN tunneling, the number of electrons pulled from the floating gate is difficult to control. When an excessive amount of electrons is pulled from the floating gate, the polarity of the floating gate becomes positive to cause over-erase. As a result, not all of the cells have the same threshold voltage Vth.
FIG. 1 is a distribution of the threshold voltage related to the cell number. Referring to FIG. 1, all of the cells on the bit lines should have the distribution like this figure, but not all of the cells have the same threshold voltage Vth. To be more specific, during the erase operation by FN tunneling, the broad distribution of the threshold voltage often causes the bit line of the flash memory generating more leakage current, even if the gates of the cells are biased with zero voltage. The cells with the threshold voltage Vth<VthL contribute to the bit line leakage. Over erase is the situation when there is bit line leakage in the flash memory cells. This bit line leakage may induce read error to the cells in program state or programming failure.
Accordingly, an over erase correction is used to raise the threshold voltage of these cells, so that the bit line leakage is reduced. During a period of the over erase correction, all of the cells on the same bit line have the same gate voltage such as 0V, that is the corresponding word lines are at 0V. In the meanwhile, drains of the cells are biased with a charge pump voltage, which is couple to the corresponding bit lines, and thus, the hot electrons are injected into the floating gate again to increase the threshold voltage of the cells. The charge pump voltage coupled to the bit lines has to sustain the needed voltage to make the over erase correction effective.
In general, the time of the over erase correction performed on all of the bit lines with the corresponding word lines at 0V is much wasted. For example, if a bit line has 256 cells, the total time of the over erase correction is about several hundred micro-seconds to mini-seconds. In order to save the time of the over erase correction, if all of the gates of the cells are biased positively, it means all of the corresponding word lines are also biased positively, the bit lines will sink a huge leakage current. However, it is possible that there is a drop in the charge pump voltage due to the huge leakage current, so that the charge pump voltage is insufficient. For example, if the drop reduces the charge pump voltage to become lower than 3 voltages, the over erase correction is ineffective.